標題: Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
作者: Ker, MD
Jiang, HC
Peng, JJ
Shieh, TL
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2001
摘要: A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.
URI: http://hdl.handle.net/11536/19091
ISBN: 0-7803-7057-0
期刊: ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS
起始頁: 113
結束頁: 116
Appears in Collections:Conferences Paper