Title on flip-flop inference in HDL synthesis

Abstract

In HDL synthesis at register transfer level (RTL), edge-triggered flip-flops are inferred to keep the consistence of the memory semantics between the target synthesized netlist and the original design written in hardware description language (HDL). Since typical synthesizers use ad hoc method to solve the flip-flop inference problem, either superfluous flip-flops or unreasonable limitations on coding style are necessary. Even worse, the ad hoc algorithms adopted by the typical synthesizers could incur the mismatches between synthesis and simulation. In this paper, we propose a uniform framework based on a concept called MC flip-flop to infer flip-flops systematically and correctly. Our approach does not impose limitations on coding style and does not infer superfluous flip-flops. Furthermore, it does not suffer from the mismatches between synthesis and simulation and can synthesize the HDL descriptions that cannot be synthesized by typical synthesizers.