Early-late gate receiving for Bluetooth packet

Full metadata record

DC Field	Value	Language
dc.contributor.author	Peng, CS	en_US
dc.contributor.author	Chang, MH	en_US
dc.contributor.author	Wen, KA	en_US
dc.date.accessioned	2014-12-08T15:26:55Z	-
dc.date.available	2014-12-08T15:26:55Z	-
dc.date.issued	2001	en_US
dc.identifier.isbn	0-7803-6412-0	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19156	-
dc.description.abstract	An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of Analog-to-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.	en_US
dc.language.iso	en_US	en_US
dc.title	Early-late gate receiving for Bluetooth packet	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS	en_US
dc.citation.spage	57	en_US
dc.citation.epage	60	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000169941100015	-
Appears in Collections:	Conferences Paper