完整後設資料紀錄
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dc.contributor.authorPeng, CSen_US
dc.contributor.authorChang, MHen_US
dc.contributor.authorWen, KAen_US
dc.date.accessioned2014-12-08T15:26:55Z-
dc.date.available2014-12-08T15:26:55Z-
dc.date.issued2001en_US
dc.identifier.isbn0-7803-6412-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/19156-
dc.description.abstractAn efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of Analog-to-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.en_US
dc.language.isoen_USen_US
dc.titleEarly-late gate receiving for Bluetooth packeten_US
dc.typeProceedings Paperen_US
dc.identifier.journal2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage57en_US
dc.citation.epage60en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000169941100015-
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