標題: | Early-late gate receiving for Bluetooth packet |
作者: | Peng, CS Chang, MH Wen, KA 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2001 |
摘要: | An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of Analog-to-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis. |
URI: | http://hdl.handle.net/11536/19156 |
ISBN: | 0-7803-6412-0 |
期刊: | 2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS |
起始頁: | 57 |
結束頁: | 60 |
顯示於類別: | 會議論文 |