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dc.contributor.authorChang, YWen_US
dc.contributor.authorChang, YTen_US
dc.date.accessioned2014-12-08T15:27:04Z-
dc.date.available2014-12-08T15:27:04Z-
dc.date.issued2000en_US
dc.identifier.isbn0-7803-6315-9en_US
dc.identifier.issn0738-100Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/19280-
dc.description.abstractFPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, congestion, etc) based on geometric distance and/or channel density is no longer accurate for FPGAs. Researchers have shown that the number of segments, instead of geometric (Manhattan) distance, traveled by a net is the most crucial factor in controlling the routing delay and cost in an FPGA. Further, the congestion information of a routing channel shall be measured by the available segments of specific lengths, instead of the density in a channel alone. In this paper, we propose an architecture-driven metric for simultaneous FPGA placement and global routing. The new metric considers the available segments and their lengths to optimize the wiring cost for placement and global routing. Experiments by employing a cluster growth placement and maze routing to demonstrate the new metric show respective average reductions of 8%, 20%, and 19% in the number of tracks used (area), maximum net delay, and average net delay based on the Lucent Technologies ORCA2C-like and the Xilinx XC4000EX-like architectures, compared with the traditional metric of geometric distance and channel density.en_US
dc.language.isoen_USen_US
dc.titleAn architecture-driven metric for simultaneous placement and global routing for FPGAsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal37TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2000en_US
dc.citation.spage567en_US
dc.citation.epage572en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000166739300105-
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