完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chih, JC | en_US |
dc.contributor.author | Chen, SG | en_US |
dc.date.accessioned | 2014-12-08T15:27:05Z | - |
dc.date.available | 2014-12-08T15:27:05Z | - |
dc.date.issued | 2000 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19300 | - |
dc.description.abstract | This work proposes a new CORDIC algorithm, which considerably reduces rotation number. It is achieved by combining several design techniques. Particularly, a new angle recoding scheme for table lookup is developed to speed up the convergence rate of the rotation angle. The required lookup table is small. Other design techniques used include: the leading-one bit detection, the variable-scale-factor compensation algorithm [6]. The number of the shift-and-add operations required in the compensation algorithm can be also further reduced by using the same residue recoding scheme. Simulations show that in aver;ige the new design needs only 3.5; iterations to generate results with 22-bit precision, which is much less than the existing designs (normally need 22 iterations). The new encoding scheme can be applied to other iterative convergence computation function such as division operation. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A fast CORDIC algorithm based on a novel angle recoding scheme | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | en_US |
dc.citation.spage | 621 | en_US |
dc.citation.epage | 624 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000088844700156 | - |
顯示於類別: | 會議論文 |