標題: | Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration |
作者: | Wu, I-Wei Chung, Chung-Ping Shann, Jean Jyh-Jiun 資訊工程學系 Department of Computer Science |
關鍵字: | instruction set extension (ISE);customizable processor;application-specific instruction-set processor (ASIP);design space exploration;area efficient |
公開日期: | 1-九月-2011 |
摘要: | Instruction set extension (ISE) is an effective approach to improve the processor performance without tremendous modification in its core architecture. To execute ISE(s), a processor core must be augmented with a new functional unit, called application specific functional unit (ASFU), which consists of multiple hardware implementation options of ISEs (ISE_HW). Obviously, since ISE_HW increases the production cost of a processor core, minimizing the area size of ISE_HW becomes important for ISE exploration. On the other hand, because of different requirements in space and speed, ISE_HW usually has multiple hardware implementation options. Under pipeline-stage timing constrain:, some of these options may have the same performance improvement but entail different hardware costs. According to this phenomenon, the area size of ISE_HW can be reduced by performing hardware design space exploration of ISE_HW. Therefore, in this paper, we propose an ISE exploration algorithm that explores not only ISE but also the hardware design space of ISE_HW. Compared with the previous research, our approach resulted in significant improvement in area efficiency and the execution performance. |
URI: | http://hdl.handle.net/11536/19326 |
ISSN: | 1016-2364 |
期刊: | JOURNAL OF INFORMATION SCIENCE AND ENGINEERING |
Volume: | 27 |
Issue: | 5 |
起始頁: | 1641 |
結束頁: | 1657 |
顯示於類別: | 期刊論文 |