Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Tsai, WC | en_US |
dc.contributor.author | Wang, SJ | en_US |
dc.date.accessioned | 2014-12-08T15:27:06Z | - |
dc.date.available | 2014-12-08T15:27:06Z | - |
dc.date.issued | 2000 | en_US |
dc.identifier.isbn | 0-7803-5747-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19338 | - |
dc.description.abstract | This article presents a new systolic architecture for the main operation in an elliptic curve cryptosystem over the finite field GF(2(m)). This proposed architecture is actually a finite field multiplier and is used to implement the addition operation in the elliptic curs-e cryptosystem. We apply partitioning scheme and parallelize the main operation in a straightforward systolic architecture to speed up the operation and then apply merging and re-timing schemes in the partitioned architecture to future improve the performance of this architecture. We compare this architecture with some previously proposed systolic architectures for the finite field arithmetics. The comparison shows that our architecture offers the lowest hardware complexity. This architectures can be easily adopted to build a low-complexity elliptic curve cryptosystem. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A systolic architecture for elliptic curve cryptosystems | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2000 5TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS, VOLS I-III | en_US |
dc.citation.spage | 591 | en_US |
dc.citation.epage | 597 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000166107600131 | - |
Appears in Collections: | Conferences Paper |