A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMS

Abstract

A novel 1.5-bit (3-level)/cell storage technique is described. This sense amplifier of DRAM can sense the ternary state. Thus, this structure can effectively reduce the bit-cost. The proposed DRAM can be operated at 1.5V without changing the common DRAM process.