完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLee, YYen_US
dc.contributor.authorLo, PCen_US
dc.date.accessioned2014-12-08T15:27:17Z-
dc.date.available2014-12-08T15:27:17Z-
dc.date.issued1998en_US
dc.identifier.isbn0-7803-4325-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/19524-
dc.description.abstractThis paper presents a new method of implementing the fast Fourier transform (FFT), the "real-time FFT algorithm", which efficiently utilizes the computer time to perform the FFT computation while the data acquisition proceeds. The main idea is to build the local butterfly modules using the data points available. The algorithm is based on the decimation-in-time split-radix FFT (DIT sr-FFT) butterfly structure. The algorithm is superior to the conventional whole-block FET algorithm in synchronizing with the on-line process. The time delay is about 2/r that of the whole-block algorithm considering the FFT size N=2(r).en_US
dc.language.isoen_USen_US
dc.titleAn efficient FFT algorithm based on building on-line butterfly sub-structureen_US
dc.typeProceedings Paperen_US
dc.identifier.journalICSP '98: 1998 FOURTH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, PROCEEDINGS, VOLS I AND IIen_US
dc.citation.spage97en_US
dc.citation.epage100en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000081007500025-
顯示於類別:會議論文