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dc.contributor.authorYu, PCen_US
dc.contributor.authorWu, JCen_US
dc.date.accessioned2014-12-08T15:27:18Z-
dc.date.available2014-12-08T15:27:18Z-
dc.date.issued1998en_US
dc.identifier.isbn0-7803-4455-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/19551-
dc.description.abstractThis paper describes the design of a Class-B output buffer for driving large capacitance load in flat panel display. Due to the large number of output buffers on a column driver chip, the quiescent current of the output buffer must be reduced. A comparator which produces full-swing output is used in the negative feedback path to eliminate quiescent current in the last stage. The proposed circuit was implemented in a 0.8 mu m CMOS process. The measured maximum static current is 54 mu A. With 5V supply voltage and 600pF load, the tracking error voltage is less than +/-8mV and the output swing is from 0.5V to 5V. The settling time for 4V swing to 0.2% is 8 mu s, which is more than adequate for driving 1204*1280 pixels LCD panel with 86Hz frame rate.en_US
dc.language.isoen_USen_US
dc.titleNovel low power Class-B output bufferen_US
dc.typeProceedings Paperen_US
dc.identifier.journalISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6en_US
dc.citation.spageE633en_US
dc.citation.epageE636en_US
dc.contributor.department電機學院zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000075224600884-
Appears in Collections:Conferences Paper