標題: Buffer size optimization for full-search block matching algorithms
作者: Yeh, YH
Lee, CY
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
公開日期: 1997
摘要: This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buffer size under minimal I/O bandwidth constraint As a result a systematic design procedure for buffer optimization is derived to reduce realization cost.
URI: http://hdl.handle.net/11536/19699
ISBN: 0-8186-7958-1
ISSN: 1063-6862
期刊: IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, PROCEEDINGS
起始頁: 76
結束頁: 85
Appears in Collections:Conferences Paper