Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cheng, SC | en_US |
dc.contributor.author | Hang, HM | en_US |
dc.date.accessioned | 2014-12-08T15:27:27Z | - |
dc.date.available | 2014-12-08T15:27:27Z | - |
dc.date.issued | 1997 | en_US |
dc.identifier.isbn | 0-8186-8183-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19711 | - |
dc.description.abstract | This paper presents an evaluation of rate control algorithms from a system-level VLSI design viewpoint. Rate control in video coding has a significant influence on the coded bits and image quality. Many rate control algorithms have been proposed mainly focusing on the optimal rate-distortion performance without considering their overall performance on the VLSI implementation. However, a system-level designer should design an algorithm not only good in performance but also good in implementation. In this paper, three different types of popular rate control algorithms have been analyzed based on their picture quality, the internal buffer size and the hardware cost. The methodology and results presented here should provide useful guidelines for selecting an appropriate rate control algorithm for system-level VLSI design. | en_US |
dc.language.iso | en_US | en_US |
dc.title | The impact of rate control algorithms on video codec hardware design | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | INTERNATIONAL CONFERENCE ON IMAGE PROCESSING - PROCEEDINGS, VOL II | en_US |
dc.citation.spage | 807 | en_US |
dc.citation.epage | 810 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1997BJ90B00204 | - |
Appears in Collections: | Conferences Paper |