完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lan, JF | en_US |
dc.contributor.author | Wu, CY | en_US |
dc.date.accessioned | 2014-12-08T15:27:27Z | - |
dc.date.available | 2014-12-08T15:27:27Z | - |
dc.date.issued | 1997 | en_US |
dc.identifier.isbn | 0-7803-3583-X | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19715 | - |
dc.description.abstract | In this paper, a multi-chip expandable modified feedforward Hamming neural network for pattern classification is designed and implemented. In the proposed modified Hamming network, the outstar circuit is used to provide the on-chip learning capability. Moreover, the embedded ratio memory in the outstar circuit is used to store the learned pattern. The chips can be connected to form pattern, element, and pattern-and-element-mixed expansions. The experimental results have been correctly verified the operation of multi-chip expansion and classification function. The contrast enhancement characteristic of the stored pattern in the 3-chip element expansion has also been observed. | en_US |
dc.language.iso | en_US | en_US |
dc.title | The multi-chip design of analog CMOS expandable modified Hamming neural network with on-chip learning and storage for pattern classification | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | en_US |
dc.citation.spage | 565 | en_US |
dc.citation.epage | 568 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1997BJ47Z00142 | - |
顯示於類別: | 會議論文 |