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dc.contributor.authorLan, JFen_US
dc.contributor.authorWu, CYen_US
dc.date.accessioned2014-12-08T15:27:27Z-
dc.date.available2014-12-08T15:27:27Z-
dc.date.issued1997en_US
dc.identifier.isbn0-7803-3583-Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/19715-
dc.description.abstractIn this paper, a multi-chip expandable modified feedforward Hamming neural network for pattern classification is designed and implemented. In the proposed modified Hamming network, the outstar circuit is used to provide the on-chip learning capability. Moreover, the embedded ratio memory in the outstar circuit is used to store the learned pattern. The chips can be connected to form pattern, element, and pattern-and-element-mixed expansions. The experimental results have been correctly verified the operation of multi-chip expansion and classification function. The contrast enhancement characteristic of the stored pattern in the 3-chip element expansion has also been observed.en_US
dc.language.isoen_USen_US
dc.titleThe multi-chip design of analog CMOS expandable modified Hamming neural network with on-chip learning and storage for pattern classificationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGEen_US
dc.citation.spage565en_US
dc.citation.epage568en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1997BJ47Z00142-
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