New VLSI architectures of RSA public-key cryptosystem

Abstract

In this paper, we propose several new VLSI architectures to reduce the hardware complexity and to increase the computation speed of the RSA Public-Key Cryptosystem. BY applying LSB-first algorithm in modular exponentiation, a different pipelining method is presented for area optimization. We modified the Montgomery algorithm in two way: (1) interleave each iteration to pipeline the critical path and (2) update the parallel input on every cycle for serial squaring. The first technique implies that the minimum cycle time can be reduced to approximately one half as before, and the second technique enables more efficient computations. We compare our architectures with the previously proposed architectures and found that our architectures offer a factor of two reduction in Area-Time product.