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dc.contributor.authorLin, Yen-Hungen_US
dc.contributor.authorChang, Shu-Hsinen_US
dc.contributor.authorLi, Yih-Langen_US
dc.date.accessioned2014-12-08T15:27:29Z-
dc.date.available2014-12-08T15:27:29Z-
dc.date.issued2011-09-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2011.2150222en_US
dc.identifier.urihttp://hdl.handle.net/11536/19748-
dc.description.abstractFor modern designs, delay optimization significantly facilitates success in design closure owing to its more realistic metric than wirelength in routing. Obstacle-avoiding rectilinear Steiner tree (OARST) construction is an essential routing problem. With the trends toward Internet protocol-block-based system-on-chip designs, OARST with buffer insertion has been surveyed to diminish the delay of long wires. Previous works on performance-driven (PD) OARST without and with buffer insertion can only handle small circuits. This paper develops a novel routing algorithm in obstacle-avoiding spanning graph to construct OARST with optimized delay efficiently. The proposed multisource single-target maze routing is first employed to identify the critical trunks, and the critical-trunk-based tree growth mechanism connects the unconnected pins to critical trunks under delay constraints of every sink. We apply the proposed critical-trunk-based tree growth mechanism to solve PD and slack-driven (SD) OARST problems. The proposed algorithms are extended to consider buffer insertion during PD and SD OARST constructions. Experimental results demonstrate that the proposed algorithms achieve an average 25.84% improvement in the maximum delay over obstacle-avoiding rectilinear Steiner minimal tree in the PD OARST problem and successfully solve 66.67% worst negative slack violations in the SD OARST problem. Compared to the simultaneous routing and buffer insertion approach, the proposed buffer-aware (BA) algorithm generates satisfactory timing results with almost identical wire length (WL). Moreover, the proposed BA SD OARST algorithm utilizes less WL than the BA rectilinear Steiner tree construction does by 17.99% on average. The runtime comparison with previous works shows the efficiency and scalability of this paper.en_US
dc.language.isoen_USen_US
dc.subjectBuffer insertionen_US
dc.subjectElmore delay modelen_US
dc.subjectobstacle-avoiding rectilinear Steiner treeen_US
dc.subjectperformance-driven routingen_US
dc.subjecttiming constrainten_US
dc.titleCritical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimizationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2011.2150222en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume30en_US
dc.citation.issue9en_US
dc.citation.spage1335en_US
dc.citation.epage1348en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000294132100006-
dc.citation.woscount0-
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