Optimization of PVD Ti/CVD TiN liner for 0.35 mu m tungsten plug technology

Abstract

A novel plasma enhanced CVD TiN process was integrated with high density plasma sputter etch preclean (PCII) and 1:1.5 collimated PVD Ti (c-PVD Ti) process to deposit a Ti/TiN liner for tungsten contact and via plugs. The integrated liner process was optimized for a 0.35 mu m non-salicide CMOS device application. RF power and sputter depth used for contact preclean were the major process Variants affecting the contact resistance, junction leakage and transistor threshold voltage. Low contact resistance was obtained for a c-PVD Ti thickness of similar to 375 Angstrom. Via resistance was significantly lower with c-PVD Ti/CVD TiN liner as compared to only a TiN liner. Contact resistance for c-PVD Ti/c-PVD TIN and c-PVD Ti/CVD TiN liners were comparable while contacts with conventional PVD Ti/TiN liner showed significantly higher values due to poor step coverage. Low junction leakage current was obtained for integrated c-PVD Ti/CVD TiN stack.