Scalable VLSI architectures for full-search block matching algorithms

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Yeh, YH	en_US
dc.contributor.author	Lee, CY	en_US
dc.date.accessioned	2014-12-08T15:27:33Z	-
dc.date.available	2014-12-08T15:27:33Z	-
dc.date.issued	1996	en_US
dc.identifier.isbn	0-7803-3259-8	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19796	-
dc.language.iso	en_US	en_US
dc.title	Scalable VLSI architectures for full-search block matching algorithms	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, PROCEEDINGS - VOL II	en_US
dc.citation.spage	1035	en_US
dc.citation.epage	1038	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1996BG63F00258	-
顯示於類別：	會議論文