A cost-effective VLSI architecture for high-throughput sequential decoder

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lee, CY	en_US
dc.date.accessioned	2014-12-08T15:27:34Z	-
dc.date.available	2014-12-08T15:27:34Z	-
dc.date.issued	1996	en_US
dc.identifier.isbn	0-7803-3073-0	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19806	-
dc.language.iso	en_US	en_US
dc.title	A cost-effective VLSI architecture for high-throughput sequential decoder	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4	en_US
dc.citation.spage	328	en_US
dc.citation.epage	331	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1996BG15V00084	-
顯示於類別：	會議論文