完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yang, CC | en_US |
dc.contributor.author | Jen, CW | en_US |
dc.contributor.author | Chang, TS | en_US |
dc.date.accessioned | 2014-12-08T15:27:38Z | - |
dc.date.available | 2014-12-08T15:27:38Z | - |
dc.date.issued | 1996 | en_US |
dc.identifier.isbn | 0-7803-3702-6 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19887 | - |
dc.description.abstract | In this paper, we proposed a new algorithm based on Montgomery's algorithm[1] to calculate modular multiplication that is the core arithmetic operation in RSA cryptosystem. Since the critical path delay in modular multiplication operation is reduced the new design yields a very fast implementation. We have implemented a 512-bit single chip RSA processor based on our modified algorithm with Compass 0.6 mu n SPDM cell library. By our modified modular exponentiation algorithm if takes about 1.5n(2) clock cycles to finish one n-bit RSA modular exponentiation operation in our architecture. The simulation results show that we can operate up to 125Mhz, therefore the baud rate of our 512-bit RSA processor is about 164k bits/sec. | en_US |
dc.language.iso | en_US | en_US |
dc.title | The IC design of a high speed RSA processor | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96 | en_US |
dc.citation.spage | 33 | en_US |
dc.citation.epage | 36 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1996BH25U00010 | - |
顯示於類別: | 會議論文 |