Data line driver design for a 10'' 480x640x3 color FED

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Wang, CC	en_US
dc.contributor.author	Wu, JC	en_US
dc.contributor.author	Huang, CM	en_US
dc.date.accessioned	2014-12-08T15:27:38Z	-
dc.date.available	2014-12-08T15:27:38Z	-
dc.date.issued	1996	en_US
dc.identifier.isbn	0-7803-3594-5	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19905	-
dc.description.abstract	A data line driver with 120 outputs and capable of producing contrast ratio over 100 for a 10'' 480x(640x3) pixels color field emission display (FED) panel have been designed. Three phase clocks were used to reduce the maximum operating frequency to 22.68Mhz. A class AB Op Amp was used as the analog output buffer to reduce the power dissipation. The chip is implemented in a 24V CMOS process, chip size is 7620 mu m x 17500 mu m.	en_US
dc.language.iso	en_US	en_US
dc.title	Data line driver design for a 10'' 480x640x3 color FED	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	IVMC '96 - 9TH INTERNATIONAL VACUUM MICROELECTRONICS CONFERENCE, TECHNICAL DIGEST	en_US
dc.citation.spage	557	en_US
dc.citation.epage	561	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1996BJ05U00126	-
顯示於類別：	會議論文