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dc.contributor.authorLin, SYen_US
dc.date.accessioned2014-12-08T15:27:43Z-
dc.date.available2014-12-08T15:27:43Z-
dc.date.issued1995en_US
dc.identifier.isbn0-08-042371-Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/19973-
dc.language.isoen_USen_US
dc.subjectnonlinear systemsen_US
dc.subjectreceding horizon controlen_US
dc.subjectVLSI array processorsen_US
dc.subjectoptimizationen_US
dc.titleArchitecture and operations of the VLSI array processors for implementing a receding horizon controlleren_US
dc.typeProceedings Paperen_US
dc.identifier.journalNONLINEAR CONTROL SYSTEMS DESIGN 1995, VOLS 1 AND 2en_US
dc.citation.spage789en_US
dc.citation.epage794en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:A1995BF64Y00130-
Appears in Collections:Conferences Paper