標題: A hardware-efficient architecture for 3-D graphics processor
作者: Liang, BS
Nieh, YC
Niou, YP
Jen, CW
Chuang, G
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
公開日期: 1995
摘要: In 3-D graphics processor, large associated information per pixel cause storage and bus transfer problems in pixel operations. In this paper, we explore the parallelisms in pixel information to design a hardware-efficient architecture, hence the hardware cost of redundant registers in pipeline stages and unnecessary bus transfer can be saved.
URI: http://hdl.handle.net/11536/20054
ISBN: 0-7803-4131-7
期刊: 1997 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS
起始頁: 88
結束頁: 92
顯示於類別:會議論文