A hardware-efficient architecture for 3-D graphics processor

dc.citation.epage	92	en_US
dc.citation.spage	88	en_US
dc.contributor.author	Liang, BS	en_US
dc.contributor.author	Nieh, YC	en_US
dc.contributor.author	Niou, YP	en_US
dc.contributor.author	Jen, CW	en_US
dc.contributor.author	Chuang, G	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:27:49Z
dc.date.available	2014-12-08T15:27:49Z
dc.date.issued	1995	en_US
dc.description.abstract	In 3-D graphics processor, large associated information per pixel cause storage and bus transfer problems in pixel operations. In this paper, we explore the parallelisms in pixel information to design a hardware-efficient architecture, hence the hardware cost of redundant registers in pipeline stages and unnecessary bus transfer can be saved.	en_US
dc.identifier.isbn	0-7803-4131-7	en_US
dc.identifier.journal	1997 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/20054
dc.identifier.wosnumber	WOS:A1995BJ34C00020
dc.language.iso	en_US	en_US
dc.title	A hardware-efficient architecture for 3-D graphics processor	en_US
dc.type	Proceedings Paper	en_US

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