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dc.contributor.authorLee, Chieh-Juien_US
dc.contributor.authorLiu, Sean Shih-Yingen_US
dc.contributor.authorHuang, Chuan-Chiaen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.contributor.authorLin, Chang-Tzuen_US
dc.contributor.authorLee, Chia-Hsinen_US
dc.date.accessioned2014-12-08T15:28:05Z-
dc.date.available2014-12-08T15:28:05Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4673-1036-9en_US
dc.identifier.issn1948-3295en_US
dc.identifier.urihttp://hdl.handle.net/11536/20352-
dc.description.abstractIn this paper, we propose a methodology that synthesize and optimize the power network for design with multiple power domains. An architecture is presented to represent the power network with presence of sleep transistors. The power network is numerically modeled to RC network using Modified Nodal Analysis and solved using Conjugate Gradient Method. Regarding to IR drop effect mitigation, an optimization technique is proposed based on Simulated Annealing that minimize total power stripe area while satisfying a given IR drop constraint. In consideration of multiple power domains, the given power domains are represented in tree-like structure and our algorithm is recursively applied to synthesize and optimize the power network for each power domain in a hierarchical fashion. The proposed methodology is integrated to commercial design tool and experimented on real design case for evaluation. To ensure practical aspect of our approach, evaluation is performed on latest digital design commercial tool. Design data and parameters are extracted using Open Access. The result of our algorithm is fed back to latest commercial tool for final IR and EM analysis. Our algorithm is tested on both industrial testcase and academic MCNC benchmark. Comparing to conventional P/G network, using our power network synthesis can achieve 31% - 35% reduction in total P/G area while satisfying maximum 10% IR-drop constraint.en_US
dc.language.isoen_USen_US
dc.titleHierarchical Power Network Synthesis for Multiple Power Domain Designsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED)en_US
dc.citation.spage477en_US
dc.citation.epage482en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000309266000069-
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