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dc.contributor.authorFan, Ming-Longen_US
dc.contributor.authorHu, Vita Pi-Hoen_US
dc.contributor.authorChen, Yin-Nienen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2014-12-08T15:28:05Z-
dc.date.available2014-12-08T15:28:05Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4577-1679-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/20361-
dc.description.abstractThis paper analyzes the impacts of single trap induced Random Telegraph Noise (RTN) on scaled FiriFET devices in tied-gate and independent-gate modes, 6T SRAM cell and logic circuits. The dependence of RTN amplitude on trap location, EOT and temperature is evaluated through 3D atomistic TCAD simulations. It is observed that charged trap located near the bottom of sidewall (gate) interface, in the middle region between the source/drain results in most significant impact. EOT scaling and higher temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependency on the location of the trap and current conduction path are analyzed. We show that planar BULK device, with larger Subthreshold Swing (S.S.) and comparable trap-induced V-T shift (Delta V-T), exhibits less nominal RTN degradation than FinFET for trap placed in the worst position. However, the larger variability and surface conduction characteristic of planar BULK device result in broader dispersion and larger worst-case degradation than FinFET with smaller variability and volume conduction inside the silicon fin. For FiriFET 6T SRAM cell, the READ Static Noise Margin (RSNM) of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the relative importance of RTN on the cell stability increases. The leakage/delay of FinFET inverter, 2-Way NAND and 2-To-1 multiplexer are investigated using mixed-mode TCAD simulations. The existence of RTN is found to cause similar to 24-27% and 13-15% variation in leakage and delay at V-dd=0.4V, respectively, for the logic circuits evaluated.en_US
dc.language.isoen_USen_US
dc.subjectFinFETen_US
dc.subjectRandom Telegraph Noiseen_US
dc.subjectSRAMen_US
dc.subjectLogic Circuitsen_US
dc.titleImpacts of Random Telegraph Noise on FinFET Devices, 6T SRAM cell, and Logic Circuitsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000309183100116-
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