標題: An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array
作者: Lin, Geng-Cing
Wang, Shao-Cheng
Lin, Yi-Wei
Tsai, Ming-Chien
Chuang, Ching-Te
Jou, Shyh-Jye
Lien, Nan-Chun
Shih, Wei-Chiang
Lee, Kuen-Di
Chu, Jyun-Kai
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2012
摘要: We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTH measurement scheme is about 2-7mV at TT corner across temperature range from 85 degrees C to -45 degrees C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.
URI: http://hdl.handle.net/11536/21578
ISBN: 978-1-4673-0219-7
ISSN: 0271-4302
期刊: 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)
起始頁: 2485
結束頁: 2488
Appears in Collections:Conferences Paper