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dc.contributor.authorLee, Jui-Shengen_US
dc.contributor.authorWang, Sheng-Hanen_US
dc.contributor.authorChou, Chih-Taien_US
dc.contributor.authorChien, Cheng-Anen_US
dc.contributor.authorChang, Hsiu-Chengen_US
dc.contributor.authorGuo, Jiun-Inen_US
dc.date.accessioned2014-12-08T15:30:54Z-
dc.date.available2014-12-08T15:30:54Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4673-4863-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/22064-
dc.description.abstractIn this paper we propose a low-bandwidth two-level inter-frame/ inter-view cache architecture for a view scalable multi-view video decoder, which adopts two decoder cores to decode multi-view videos in parallel. The first level L1 cache is developed for the single video decoder core, which is able to reduce 60% bandwidth in doing inter-frame prediction in average. Moreover, we develop the second level L2 cache architecture to reuse the same reference data for doing interview prediction among different decoder cores, which can further reduce 35% bandwidth. By adopting the proposed two-level cache architecture for doing inter-frame/ inter-view prediction, we can reduce 80% bandwidth through a view scalable multi-view video decoder implementation, which achieves real-time HD1080 dual-view video decoding.en_US
dc.language.isoen_USen_US
dc.titleAn Inter-frame/Inter-view Cache Architecture Design for Multi-view Video Decodersen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA ASC)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000319456200221-
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