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dc.contributor.authorGhosh, Amlanen_US
dc.contributor.authorRao, Rahul M.en_US
dc.contributor.authorKim, Jae-Joonen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.contributor.authorBrown, Richard B.en_US
dc.date.accessioned2014-12-08T15:31:54Z-
dc.date.available2014-12-08T15:31:54Z-
dc.date.issued2013-09-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2012.2218838en_US
dc.identifier.urihttp://hdl.handle.net/11536/22536-
dc.description.abstractThe need for efficient and accurate detection schemes to assess the impact of process variations on the parametric yield of integrated circuits has increased in the nanometer design era. In this paper, the difference of rise and fall slew is presented as another process-variation metric along with the delay in determining the relative mismatch between the drive strengths of nMOS and pMOS devices. The importance of considering both of these metrics is illustrated, and a new slew-rate monitoring circuit is presented for measuring the difference of rise and fall slew of a signal on the critical path of a circuit. Sensitivity analysis with multiple pulses as input has also been investigated. Bias generator circuits that track nMOS and pMOS threshold voltages have been incorporated, which makes the design less susceptible to process variation. Design considerations, simulation results, and characteristics of the slew-rate monitor circuitry in a 65-nm IBM CMOS process are presented, and a sensitivity of 50 MHz/50 ps for single pulse input is achieved. The measurement sensitivity of a fabricated slew-rate monitor in a 65-nm IBM CMOS technology is 0.11 V/mu s, with 1089 pF as the output load of the slew-rate monitor.en_US
dc.language.isoen_USen_US
dc.subjectProcess variation compensationen_US
dc.subjectprocess variation detectionen_US
dc.subjectslewen_US
dc.subjectslew-rate monitoren_US
dc.titleSlew-Rate Monitoring Circuit for On-Chip Process Variation Detectionen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TVLSI.2012.2218838en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume21en_US
dc.citation.issue9en_US
dc.citation.spage1683en_US
dc.citation.epage1692en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000322830200010-
dc.citation.woscount1-
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