Test and Analysis of the ESD Robustness for the Diode-Connected a-IGZO Thin Film Transistors

doi:10.1109/JDT.2013.2257680

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DC 欄位	值	語言
dc.contributor.author	Tai, Ya-Hsiang	en_US
dc.contributor.author	Chiu, Hao-Lin	en_US
dc.contributor.author	Chou, Lu-Sheng	en_US
dc.date.accessioned	2014-12-08T15:31:59Z	-
dc.date.available	2014-12-08T15:31:59Z	-
dc.date.issued	2013-08-01	en_US
dc.identifier.issn	1551-319X	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/JDT.2013.2257680	en_US
dc.identifier.uri	http://hdl.handle.net/11536/22580	-
dc.description.abstract	In this work, wafer level TLP testing is applied to amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) to study the factors of their electrostatic discharge (ESD) robustness. Two kinds of TFTs with N2O and O-2 treatments are subject to the ESD test. It is found that the contact resistance of the TFTs, instead of the channel quality, dominates the ESD power for them to be damaged.	en_US
dc.language.iso	en_US	en_US
dc.subject	Amorphous Indium-Gallium-Zinc Oxide thin film transistor (a-IGZO TFT)	en_US
dc.subject	electrostatic discharge (ESD)	en_US
dc.title	Test and Analysis of the ESD Robustness for the Diode-Connected a-IGZO Thin Film Transistors	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/JDT.2013.2257680	en_US
dc.identifier.journal	JOURNAL OF DISPLAY TECHNOLOGY	en_US
dc.citation.volume	9	en_US
dc.citation.issue	8	en_US
dc.citation.spage	613	en_US
dc.citation.epage	618	en_US
dc.contributor.department	光電工程學系	zh_TW
dc.contributor.department	顯示科技研究所	zh_TW
dc.contributor.department	Department of Photonics	en_US
dc.contributor.department	Institute of Display	en_US
dc.identifier.wosnumber	WOS:000323334300003	-
dc.citation.woscount	1	-
顯示於類別：	期刊論文

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