Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs

Abstract

This paper discusses the design and optimization of 6T SRAM cell using multiple stacked NanoWire (NW) MOSFETs. The results suggest that RSNM reaches the maximum when Pull-Up (PU) and Pull-Down (PD) transistors are stacked in equivalent number. Up to 40% and 91% improvement in RSNM are achieved at the cost of 7.5% and 5.9% degradation in WSNM using Floating-Power Write-assist compared with the case without stacking at V-DD = 0.3V and 1V, respectively. For robust design in subthreshold SRAM, raising V-trip by stacking PU transistors is more efficient than reducing Read disturb by stacking PD transistors under the premise of using quantized number of stacked NW. Moreover, we show that the stacked NW MOSFETs suppress the impact of Line-Edge Roughness (LER) variation and mitigate the variability in SRAM.