A PARALLEL BIT-LEVEL MAXIMUM MINIMUM SELECTOR TO DIGITAL AND VIDEO SIGNAL-PROCESSING

doi:10.1109/82.329739

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	LEE, CY	en_US
dc.contributor.author	JUAN, SC	en_US
dc.contributor.author	YANG, WW	en_US
dc.date.accessioned	2014-12-08T15:03:45Z	-
dc.date.available	2014-12-08T15:03:45Z	-
dc.date.issued	1994-10-01	en_US
dc.identifier.issn	1057-7130	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/82.329739	en_US
dc.identifier.uri	http://hdl.handle.net/11536/2298	-
dc.description.abstract	This paper presents a novel circuit for parallel bit-level maximum/minimum selection. The selection is based on a label-updating scheme which sequentially scans a set of data patterns from MSB to LSB and generates corresponding labels. The complete circuit realizing this scheme consists of a set of updating units and a global OR unit, where each updating unit is composed of only a few basic gates. Due to structure modularity, the developed circuit provides a very cost-effective hardware solution for comparing large volumes of data patterns as those required in digital and video signal processing.	en_US
dc.language.iso	en_US	en_US
dc.title	A PARALLEL BIT-LEVEL MAXIMUM MINIMUM SELECTOR TO DIGITAL AND VIDEO SIGNAL-PROCESSING	en_US
dc.type	Note	en_US
dc.identifier.doi	10.1109/82.329739	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING	en_US
dc.citation.volume	41	en_US
dc.citation.issue	10	en_US
dc.citation.spage	693	en_US
dc.citation.epage	695	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1994PR11000005	-
dc.citation.woscount	2	-
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