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dc.contributor.authorChen, K. N.en_US
dc.contributor.authorYoung, A. M.en_US
dc.contributor.authorLee, S. H.en_US
dc.contributor.authorLu, J. -Q.en_US
dc.date.accessioned2014-12-08T15:33:11Z-
dc.date.available2014-12-08T15:33:11Z-
dc.date.issued2011-06-01en_US
dc.identifier.issn1533-4880en_US
dc.identifier.urihttp://dx.doi.org/10.1166/jnn.2011.4149en_US
dc.identifier.urihttp://hdl.handle.net/11536/23069-
dc.description.abstractThe integrity of bonded Cu interconnects in wafer-level three-dimensional integration has been investigated as the function of pattern size and density, as well as bonding process parameter. The desired pattern density coupled with the application of bonding process profile we developed gives optimal yield and alignment accuracy, and provides excellent electrical connectivity and contact resistance through the entire wafer. This result is a key milestone in establishing the manufacturability of Cu-based interconnections for 3D integration technology.en_US
dc.language.isoen_USen_US
dc.subjectThree-Dimensional Integrationen_US
dc.subject3D ICen_US
dc.subjectWafer Bondingen_US
dc.subjectCu Bondingen_US
dc.titleElectrical Performances and Structural Designs of Copper Bonding in Wafer-Level Three-Dimensional Integrationen_US
dc.typeArticleen_US
dc.identifier.doi10.1166/jnn.2011.4149en_US
dc.identifier.journalJOURNAL OF NANOSCIENCE AND NANOTECHNOLOGYen_US
dc.citation.volume11en_US
dc.citation.issue6en_US
dc.citation.spage5143en_US
dc.citation.epage5147en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000291568100067-
dc.citation.woscount3-
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