標題: | High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver |
作者: | Wong, Cheng-Chi Chang, Hsie-Chia 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Parallel turbo decoder;quadratic permutation polynomial (QPP) interleaver |
公開日期: | 1-六月-2011 |
摘要: | This paper presents a high-efficiency parallel architecture for a turbo decoder using a quadratic permutation polynomial (QPP) interleaver. Conventionally, two half-iterations for different component codewords alternate during the decoding flow. Due to the initialization calculation and pipeline delays in every half-iteration, the functional units in turbo decoders will be idle for several cycles. This inactive period will degrade throughput, especially for small blocks or high parallelism. To resolve this issue, we impose several constraints on the QPP interleaver and rearrange the processing schedule; then the following half-iteration can be executed before the completion of the current half-iteration. Thus, it can eliminate the idle cycles and increase the efficiency of functional units. Based on this modified schedule with 100% efficiency, a parallel turbo decoder which contains 32 radix-2(4) SISO decoders is implemented with 90 nm technology to achieve 1.4 Gb/s while decoding size-4096 blocks for 8 iterations. |
URI: | http://dx.doi.org/10.1109/TCSI.2010.2097690 http://hdl.handle.net/11536/23146 |
ISSN: | 1549-8328 |
DOI: | 10.1109/TCSI.2010.2097690 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
Volume: | 58 |
Issue: | 6 |
起始頁: | 1412 |
結束頁: | 1420 |
顯示於類別: | 期刊論文 |