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dc.contributor.authorTsai, Chang-Hungen_US
dc.contributor.authorWang, Hsiuan-Tingen_US
dc.contributor.authorLiu, Chia-Linen_US
dc.contributor.authorLi, Yaoen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:34:52Z-
dc.date.available2014-12-08T15:34:52Z-
dc.date.issued2013en_US
dc.identifier.isbn978-1-4799-0277-4978-1-4799-0280-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/23725-
dc.description.abstractAn architecture of H. 265/HEVC video decoder for next generation video applications is presented. By exploiting near-lossless data compression and Sharing Above Line Buffer (SALB) schemes, both memory bandwidth and on-chip storage can be reduced. Moreover, cross-stage scheduling is applied to the 4-stage decoding pipeline to minimize idle computations. Fabricated in 90nm 1P9M CMOS process, the test chip of the proposed H. 265/HEVC video decoder occupies an area of 1.60x1.98mm(2) to achieve 1080p@30fps and 720p@30fps real-time decoding with power consumption of 36.90 and 9.57mW.en_US
dc.language.isoen_USen_US
dc.titleA 446.6K-Gates 0.55-1.2V H.265/HEVC Decoder for Next Generation Video Applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)en_US
dc.citation.spage305en_US
dc.citation.epage308en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000330857500076-
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