A Reconfigurable Inverse Transform Architecture Design for HEVC Decoder

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chiang, Pai-Tse	en_US
dc.contributor.author	Chang, Tian Sheuan	en_US
dc.date.accessioned	2014-12-08T15:35:45Z	-
dc.date.available	2014-12-08T15:35:45Z	-
dc.date.issued	2013	en_US
dc.identifier.isbn	978-1-4673-5762-3; 978-1-4673-5760-9	en_US
dc.identifier.issn	0271-4302	en_US
dc.identifier.uri	http://hdl.handle.net/11536/24138	-
dc.description.abstract	In this paper, we present a reconfigurable hardware design which can support the inverse transform size from 4x4 to 32x32 in HEVC (High Efficiency Video Coding). We explore the coefficient properties of various inverse transforms such that a base inverse transform unit can be reconfigured or refined to generate other size of inverse transform. The implementation in 90nm technology can support 3840x2160@30fps processing and only needs about 133.8K gate count, which can save 53% of gate count when compared with previous work.	en_US
dc.language.iso	en_US	en_US
dc.title	A Reconfigurable Inverse Transform Architecture Design for HEVC Decoder	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)	en_US
dc.citation.spage	1006	en_US
dc.citation.epage	1009	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000332006801063	-
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