完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLiao, Te-Wenen_US
dc.contributor.authorSu, Jun-Renen_US
dc.contributor.authorHung, Chung-Chihen_US
dc.date.accessioned2014-12-08T15:35:45Z-
dc.date.available2014-12-08T15:35:45Z-
dc.date.issued2013en_US
dc.identifier.isbn978-1-4673-5762-3; 978-1-4673-5760-9en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/24143-
dc.description.abstractThis paper presents a low phase-noise phase locked loop (PLL) system with a Multi-Phase Over-Sampling Charge Pump (MPOSCP) for wireless applications. The low phase-noise frequency synthesizer reduces ripples and noise on the control voltage of the ring voltage-controlled oscillator (VCO) as a means to control in-band noise at the output of the PLL. An MPOSCP is proposed to perform multi-phase over-sampling control for the charge pump (CP) in locked state. The proposed frequency synthesizer was fabricated using the TSMC 90-nm CMOS process. The prototype occupies 0.046mm2 active area, the reference frequency is 27 MHz, and the output frequency is 432 MHz with the total power consumption of 7 mW. The PLL achieved phase noise below - 100 dBc/Hz from 15 Hz to 100 kHz with the reference spurs below - 48 dBc.en_US
dc.language.isoen_USen_US
dc.subjectLow Phase-Noise PLLen_US
dc.subjectRing VCOen_US
dc.subjectFrequency synthesizeren_US
dc.titleRing-VCO Based Low Noise and Low Spur Frequency Synthesizeren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage1861en_US
dc.citation.epage1864en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000332006802022-
顯示於類別:會議論文