完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liao, Te-Wen | en_US |
dc.contributor.author | Su, Jun-Ren | en_US |
dc.contributor.author | Hung, Chung-Chih | en_US |
dc.date.accessioned | 2014-12-08T15:35:45Z | - |
dc.date.available | 2014-12-08T15:35:45Z | - |
dc.date.issued | 2013 | en_US |
dc.identifier.isbn | 978-1-4673-5762-3; 978-1-4673-5760-9 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/24143 | - |
dc.description.abstract | This paper presents a low phase-noise phase locked loop (PLL) system with a Multi-Phase Over-Sampling Charge Pump (MPOSCP) for wireless applications. The low phase-noise frequency synthesizer reduces ripples and noise on the control voltage of the ring voltage-controlled oscillator (VCO) as a means to control in-band noise at the output of the PLL. An MPOSCP is proposed to perform multi-phase over-sampling control for the charge pump (CP) in locked state. The proposed frequency synthesizer was fabricated using the TSMC 90-nm CMOS process. The prototype occupies 0.046mm2 active area, the reference frequency is 27 MHz, and the output frequency is 432 MHz with the total power consumption of 7 mW. The PLL achieved phase noise below - 100 dBc/Hz from 15 Hz to 100 kHz with the reference spurs below - 48 dBc. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Low Phase-Noise PLL | en_US |
dc.subject | Ring VCO | en_US |
dc.subject | Frequency synthesizer | en_US |
dc.title | Ring-VCO Based Low Noise and Low Spur Frequency Synthesizer | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | en_US |
dc.citation.spage | 1861 | en_US |
dc.citation.epage | 1864 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000332006802022 | - |
顯示於類別: | 會議論文 |