VLSI Implementation of a Low Complexity 4x4 MIMO Sphere Decoder with Table Enumeration

Abstract

In this work a sphere decoder with low complexity is proposed and implemented. We propose a simplified norm algorithm, which is called admissible set elimination (ASE), to dramatically decrease the number of searching nodes. In addition, the decoder uses table- look-up to acquire the enumeration order of different constellations. As a result, the critical path is shortened and the throughput is enhanced. Compared to the optimal ML detector, the proposed scheme greatly improves the complexity and throughput, while the performance only degrades around 0.5 dB. The proposed scheme is fabricated by a TSMC 90 nm process. The area is 0.85 mm(2), and the average throughput can be up to 411.3 Mbps when the clock rate is 108.7 MHz.