Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hung, Shao-Hang | en_US |
dc.contributor.author | Chao, Chih-Feng | en_US |
dc.contributor.author | Yan, Yu-Chun | en_US |
dc.contributor.author | Lin, Bor-Shyh | en_US |
dc.contributor.author | Lin, Chin-Teng | en_US |
dc.date.accessioned | 2014-12-08T15:36:19Z | - |
dc.date.available | 2014-12-08T15:36:19Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-6890-4 | en_US |
dc.identifier.issn | 0886-1420 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/24657 | - |
dc.description.abstract | This paper presented Independent Component Analysis (ICA) Hard-IP integration in System on Programmable Chip (SOPC) platform. The ICA component can discover the main component for original signal in multiple fetching signal sources, and it has been used in biomedical signal processing such as electroencephalogram (EEG) analysis. The proposed system consists of a programmable CPU, ICA processing units, system bus, communication, and display interface. The experimental results showed that the proposed design implemented on Altera DE2 FPGA development board, can achieve real-time signal separation and display at 100 MHz. The whole design consists of 29,640 logic elements. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | electroencephalogram | en_US |
dc.subject | Independent Component Analysis | en_US |
dc.subject | System on Programmable Chip(SOPC) | en_US |
dc.title | Independent Component Analysis Hard-IP integration System on Programmable Chip (SOPC) Platform | en_US |
dc.type | Article | en_US |
dc.identifier.journal | TENCON 2010: 2010 IEEE REGION 10 CONFERENCE | en_US |
dc.citation.spage | 1705 | en_US |
dc.citation.epage | 1709 | en_US |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:000287978600284 | - |
Appears in Collections: | Conferences Paper |