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dc.contributor.authorTsai, Jung-Rueyen_US
dc.contributor.authorLee, Ko-Huien_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2014-12-08T15:36:25Z-
dc.date.available2014-12-08T15:36:25Z-
dc.date.issued2014-04-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.7567/JJAP.53.04ED14en_US
dc.identifier.urihttp://hdl.handle.net/11536/24751-
dc.description.abstractA novel gate-all-around (GAA) poly-Si floating-gate (FG) memory device with triangular nanowire (NW) channels was fabricated and characterized in this work. The enhanced electric field around the corners of the NW channels boosts more electrons tunneling through the tunnel oxide layer during programming and erasing (P/E) processes, and thus the operation voltage markedly decreases. Furthermore, the nonlocalized trapping feature characteristic of the FG makes the injection of electrons easier during the programming operation, which was demonstrated by technology computer-aided design (TCAD) simulations. (C) 2014 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titleGate-all-around floating-gate memory device with triangular poly-Si nanowire channelsen_US
dc.typeArticleen_US
dc.identifier.doi10.7567/JJAP.53.04ED14en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume53en_US
dc.citation.issue4en_US
dc.citation.epageen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000338185100049-
dc.citation.woscount0-
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