標題: A fully integrated 5.2-GHz single-ended-in and single-ended-out 0.18-mu m CMOS Gilbert upconverter
作者: Meng, CC
Lin, MQ
Huang, GW
電信工程研究所
Institute of Communications Engineering
關鍵字: CMOS;Gilbert upconverter;RFIC
公開日期: 5-十一月-2004
摘要: A monolithic 5.2-GHz single-ended-in and single-ended-out Gilbert upconverter with balanced operation is demonstrated using 0.18-mum deep n-well CMOS technology. Thefully matched Gilbert upconverter has conversion gain of - 11.5 dB and OPIdB of - 19 dBm when input IF = 300 MHz, LO = 4.9 GHz, and output RF = 5.2 GHz. The IF input return loss is better than 14 dB for frequencies up to 7 GHz, while RF output return loss is 15 dB at 5.2 GHz. (C) 2004 Wiley Periodicals, Inc.
URI: http://dx.doi.org/10.1002/mop.20430
http://hdl.handle.net/11536/25651
ISSN: 0895-2477
DOI: 10.1002/mop.20430
期刊: MICROWAVE AND OPTICAL TECHNOLOGY LETTERS
Volume: 43
Issue: 3
起始頁: 240
結束頁: 242
顯示於類別:期刊論文


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