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dc.contributor.authorKuo, Yu-Tingen_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorLiu, Chih-Weien_US
dc.date.accessioned2014-12-08T15:37:48Z-
dc.date.available2014-12-08T15:37:48Z-
dc.date.issued2011en_US
dc.identifier.issn1687-6172en_US
dc.identifier.urihttp://hdl.handle.net/11536/25993-
dc.identifier.urihttp://dx.doi.org/10.1155/2011/357906en_US
dc.description.abstractThe coefficient values and number representations of digital FIR filters have significant impacts on the complexity of their VLSI realizations and thus on the system cost and performance. So, making a good tradeoff between implementation costs and quantization errors is essential for designing optimal FIR filters. This paper presents our complexity-aware quantization framework of FIR filters, which allows the explicit tradeoffs between the hardware complexity and quantization error to facilitate FIR filter design exploration. A new common subexpression sharing method and systematic bit-serialization are also proposed for lightweight VLSI implementations. In our experiments, the proposed framework saves 49% similar to 51% additions of the filters with 2's complement coefficients and 10% similar to 20% of those with conventional signed-digit representations for comparable quantization errors. Moreover, the bit-serialization can reduce 33% similar to 35% silicon area for less timing-critical applications.en_US
dc.language.isoen_USen_US
dc.titleComplexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filtersen_US
dc.typeArticleen_US
dc.identifier.doi10.1155/2011/357906en_US
dc.identifier.journalEURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSINGen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000290385600001-
dc.citation.woscount1-
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