完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang, Chen-Shuo | en_US |
dc.contributor.author | Liu, Po-Tsun | en_US |
dc.date.accessioned | 2014-12-08T15:37:52Z | - |
dc.date.available | 2014-12-08T15:37:52Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.issn | 1099-0062 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/26040 | - |
dc.identifier.uri | http://dx.doi.org/10.1149/1.3551463 | en_US |
dc.description.abstract | In this study, negative-bias-temperature-instability (NBTI) stress induced interface, and bulk states of polycrystalline silicon (poly-Si) film were identified by using gated poly-Si P-intrinsic-N (PIN) diodes. The generation of reverse current was proportional to the quantity of defects in the poly-Si of the gated diode device. Experimental results revealed NBTI degradation has a spatial distribution in the poly-Si film and demonstrated that the resultant generation of poly-Si bulk states causes the elevated drain leakage current of thin-film transistors (TFTs). We conclude that grain boundaries, with enriched hydrogenated silicon bonds in the bulk of poly-Si, interact electrochemically with hole-carriers. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3551463] All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Impact of Negative-Bias-Temperature-Instability on Channel Bulk of Polysilicon TFT by Gated PIN Diode Analysis | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1149/1.3551463 | en_US |
dc.identifier.journal | ELECTROCHEMICAL AND SOLID STATE LETTERS | en_US |
dc.citation.volume | 14 | en_US |
dc.citation.issue | 5 | en_US |
dc.citation.spage | H194 | en_US |
dc.citation.epage | H196 | en_US |
dc.contributor.department | 光電工程學系 | zh_TW |
dc.contributor.department | 顯示科技研究所 | zh_TW |
dc.contributor.department | Department of Photonics | en_US |
dc.contributor.department | Institute of Display | en_US |
dc.identifier.wosnumber | WOS:000288128800023 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |