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dc.contributor.authorLin, Chun-Yuen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:38:45Z-
dc.date.available2014-12-08T15:38:45Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-5309-2en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/26521-
dc.description.abstractWith the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only similar to 200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.en_US
dc.language.isoen_USen_US
dc.title2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Low Standby Leakage in 65-nm CMOS Processen_US
dc.typeArticleen_US
dc.identifier.journal2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMSen_US
dc.citation.spage3417en_US
dc.citation.epage3420en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000287216003160-
Appears in Collections:Conferences Paper