完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, JM | en_US |
dc.contributor.author | Chang, YW | en_US |
dc.date.accessioned | 2014-12-08T15:39:05Z | - |
dc.date.available | 2014-12-08T15:39:05Z | - |
dc.date.issued | 2004-06-01 | en_US |
dc.identifier.issn | 0278-0070 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCAD.2004.828114 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/26724 | - |
dc.description.abstract | In this paper, we extend the concept of the P-admissible floorplan representation to that of the P* -admissible one. A P* -admissible representation can model the most general floorplans. Each of the currently existing P* -admissible representations, sequence pair (SP), bounded-slicing grid, and transitive closure graph (TCG), has its strengths as well as weaknesses. We show the equivalence of the two most promising P* -admissible representations, TCG and SP, and integrate TCG with a packing sequence (part of SP) into a representation, called TCG-S. TCG-S combines the advantages of SP and TCG and at the same time eliminates their disadvantages. With the property of SP, a fast packing scheme is possible. Inherited nice properties from TCG, the geometric relations among modules are transparent to TCG-S (implying faster convergence to a desired solution), placement with position constraints becomes much easier, and incremental update for cost evaluation can be realized. These nice properties make TCG-S a superior representation which exhibits an elegant solution structure to facilitate the search for a desired floorplan/placement. Extensive experiments show that TCG-S results in the best area utilization, wirelength optimization, convergence speed, and stability among existing works and is very flexible in handling placement with special constraints. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | floorplanning | en_US |
dc.subject | layout | en_US |
dc.subject | physical_design | en_US |
dc.subject | transitive_closure_graph | en_US |
dc.title | TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCAD.2004.828114 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | en_US |
dc.citation.volume | 23 | en_US |
dc.citation.issue | 6 | en_US |
dc.citation.spage | 968 | en_US |
dc.citation.epage | 980 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000221659500014 | - |
dc.citation.woscount | 17 | - |
顯示於類別: | 期刊論文 |