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dc.contributor.authorLin, JMen_US
dc.contributor.authorChang, YWen_US
dc.date.accessioned2014-12-08T15:39:05Z-
dc.date.available2014-12-08T15:39:05Z-
dc.date.issued2004-06-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2004.828114en_US
dc.identifier.urihttp://hdl.handle.net/11536/26724-
dc.description.abstractIn this paper, we extend the concept of the P-admissible floorplan representation to that of the P* -admissible one. A P* -admissible representation can model the most general floorplans. Each of the currently existing P* -admissible representations, sequence pair (SP), bounded-slicing grid, and transitive closure graph (TCG), has its strengths as well as weaknesses. We show the equivalence of the two most promising P* -admissible representations, TCG and SP, and integrate TCG with a packing sequence (part of SP) into a representation, called TCG-S. TCG-S combines the advantages of SP and TCG and at the same time eliminates their disadvantages. With the property of SP, a fast packing scheme is possible. Inherited nice properties from TCG, the geometric relations among modules are transparent to TCG-S (implying faster convergence to a desired solution), placement with position constraints becomes much easier, and incremental update for cost evaluation can be realized. These nice properties make TCG-S a superior representation which exhibits an elegant solution structure to facilitate the search for a desired floorplan/placement. Extensive experiments show that TCG-S results in the best area utilization, wirelength optimization, convergence speed, and stability among existing works and is very flexible in handling placement with special constraints.en_US
dc.language.isoen_USen_US
dc.subjectfloorplanningen_US
dc.subjectlayouten_US
dc.subjectphysical_designen_US
dc.subjecttransitive_closure_graphen_US
dc.titleTCG-S: Orthogonal coupling of P*-admissible representations for general floorplansen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2004.828114en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume23en_US
dc.citation.issue6en_US
dc.citation.spage968en_US
dc.citation.epage980en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000221659500014-
dc.citation.woscount17-
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