完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLee, CYen_US
dc.contributor.authorYang, JNen_US
dc.contributor.authorCheng, YCen_US
dc.date.accessioned2014-12-08T15:39:07Z-
dc.date.available2014-12-08T15:39:07Z-
dc.date.issued2004-06-01en_US
dc.identifier.issn0916-8516en_US
dc.identifier.urihttp://hdl.handle.net/11536/26737-
dc.description.abstractAn RF CMOS active inductor with a novel loss compensation circuit network is proposed. Performance of this active inductor can be improved by adding a novel network, which simultaneously reduces parallel and series losses. Consequently, this technique not only increases Q value, inductance, and operating frequency, but also reduces power consumption and circuit complexity. Simulation results show that better performance indices can be achieved, such as minimum total equivalent loss of 1 mOmega, maximum Q value about 3E5, and inductance value from 20 nH to 45 nH in the RF range of 0.6 GHz to 1.6 GHz. Power dissipation is around 1.76 mW under 2.5 V dc supply voltage.en_US
dc.language.isoen_USen_US
dc.subjectactive inductoren_US
dc.subjectinternal lossen_US
dc.subjectinductanceen_US
dc.subjectpower dissipationen_US
dc.subjectQ valueen_US
dc.titleImproving RF CMOS active inductor by simple loss compensation networken_US
dc.typeArticleen_US
dc.identifier.journalIEICE TRANSACTIONS ON COMMUNICATIONSen_US
dc.citation.volumeE87Ben_US
dc.citation.issue6en_US
dc.citation.spage1681en_US
dc.citation.epage1683en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000221983300027-
dc.citation.woscount2-
顯示於類別:期刊論文