Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chen, K. N.	en_US
dc.contributor.author	Shaw, T. M.	en_US
dc.contributor.author	Cabral, C., Jr.	en_US
dc.contributor.author	Zuo, G.	en_US
dc.date.accessioned	2014-12-08T15:39:16Z	-
dc.date.available	2014-12-08T15:39:16Z	-
dc.date.issued	2010	en_US
dc.identifier.isbn	978-1-4244-7419-6	en_US
dc.identifier.uri	http://hdl.handle.net/11536/26820	-
dc.description.abstract	We demonstrate a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding. Hybrid Cu-oxide hybrid bonding shows excellent bond quality and performances in terms of alignment, bond strength, and ambient permeation oxidation. Excellent performances of initial reliability and quality evaluations for Cu-oxide hybrid bonding are key milestones in proving manufacturability of 3D integration technology.	en_US
dc.language.iso	en_US	en_US
dc.title	Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding	en_US
dc.type	Article	en_US
dc.identifier.journal	2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000287997300007	-
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