完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChung, CCen_US
dc.contributor.authorLee, CYen_US
dc.date.accessioned2014-12-08T15:39:31Z-
dc.date.available2014-12-08T15:39:31Z-
dc.date.issued2004-03-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2003.822890en_US
dc.identifier.urihttp://hdl.handle.net/11536/26981-
dc.description.abstractA new DLL-based approach for all-digital multiphase clock generation is presented. By-using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all-digital and cell-based solution can overcome the false-lock problem in conventional designs. Furthermore, the proposed all-digital multiphase clock generator (ADMCG) can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity in many different applications. The test chip shows that our proposal demonstrates a wide frequency range to meet the needs of many digital. communication applications.en_US
dc.language.isoen_USen_US
dc.subjectdelay-locked loops (DLLs)en_US
dc.subjectdigitally controlled delay line (DCDL)en_US
dc.subjectmultiphase clock generationen_US
dc.subjectphase synchronizationen_US
dc.titleA new DLL-based approach for all-digital multiphase clock generationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2003.822890en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume39en_US
dc.citation.issue3en_US
dc.citation.spage469en_US
dc.citation.epage475en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000220018900008-
dc.citation.woscount34-
顯示於類別:期刊論文


文件中的檔案:

  1. 000220018900008.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。