完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ho, Chen-Kang | en_US |
dc.contributor.author | Hong, Hao-Chiao | en_US |
dc.date.accessioned | 2014-12-08T15:41:09Z | - |
dc.date.available | 2014-12-08T15:41:09Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.isbn | 978-1-4244-2781-9 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/27998 | - |
dc.description.abstract | This paper demonstrates a 6-GS/s 6-bit flash ADC and current-steering DAC pair in 0.13 mu m CMOS. Averaging and interpolating techniques are applied to reduce the offsets and to save the power of the ADC. Current mode logics are used to achieve a high speed and to overcome the severe power bouncing issue. Design-for-testability circuits are added to conduct the at-speed tests by internally cascading the ADC and DAC. The cascaded ADC and DAC pair clocked at 6GHz achieves a 37.0 dB signal-to-noise ratio and a 26.0 dBc spurious-free dynamic range with the -1 dBFS, 502 MHz stimulus. The ADC and DAC consumes 655 mW and 115 mW from a 1.2-V supply, respectively. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | flash ADC | en_US |
dc.subject | DAC | en_US |
dc.subject | at-speed tests | en_US |
dc.subject | GS/s | en_US |
dc.title | A 6-GS/s, 6-bit, At-speed Testable ADC and DAC Pair in 0.13 mu m CMOS | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM | en_US |
dc.citation.spage | 207 | en_US |
dc.citation.epage | 210 | en_US |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:000271941200052 | - |
顯示於類別: | 會議論文 |