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DC 欄位語言
dc.contributor.authorHo, Chen-Kangen_US
dc.contributor.authorHong, Hao-Chiaoen_US
dc.date.accessioned2014-12-08T15:41:09Z-
dc.date.available2014-12-08T15:41:09Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-2781-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/27998-
dc.description.abstractThis paper demonstrates a 6-GS/s 6-bit flash ADC and current-steering DAC pair in 0.13 mu m CMOS. Averaging and interpolating techniques are applied to reduce the offsets and to save the power of the ADC. Current mode logics are used to achieve a high speed and to overcome the severe power bouncing issue. Design-for-testability circuits are added to conduct the at-speed tests by internally cascading the ADC and DAC. The cascaded ADC and DAC pair clocked at 6GHz achieves a 37.0 dB signal-to-noise ratio and a 26.0 dBc spurious-free dynamic range with the -1 dBFS, 502 MHz stimulus. The ADC and DAC consumes 655 mW and 115 mW from a 1.2-V supply, respectively.en_US
dc.language.isoen_USen_US
dc.subjectflash ADCen_US
dc.subjectDACen_US
dc.subjectat-speed testsen_US
dc.subjectGS/sen_US
dc.titleA 6-GS/s, 6-bit, At-speed Testable ADC and DAC Pair in 0.13 mu m CMOSen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAMen_US
dc.citation.spage207en_US
dc.citation.epage210en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000271941200052-
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